A current mode voltage regulator regulates an output voltage by regulating the current through an inductor. The regulator uses both a relatively fast current feedback loop (which senses current) and a slower voltage feedback loop (which senses voltage) to control the output voltage. Due to phase shifting and delays in the feedback loops, stability is a concern. Oscillations may be avoided by selecting compensation components connected to the voltage feedback loop, such as a capacitor-resistor network, which attenuate the loop gain above a certain frequency and provide a desired phase shift. The optimum component values are determined based on the final design of the regulator, and the user is typically required to calculate or manually test and decide on the optimum component values. One method of compensating the regulator is to add a capacitor-resistor network external to the regulator chip at the output of an error amplifier. However, this requires the user to optimize the regulator manually to have a desired phase margin at a desired unity gain frequency (cross-over frequency) of the feedback loop, and the complexity of optimizing performance of the regulator is typically outside the skill level of the users who are not experienced power supply designers.
It is not desirable to simply compensate the regulator using predetermined component values to guarantee stability under worst case conditions (e.g., parameter variations over time), since the transient performance cannot be optimized.
Therefore, what is needed is a fast auto-compensation technique that automatically tests (identifies) the initial characteristics of a current mode voltage regulator, then automatically adjusts the characteristics of the regulator to optimally compensate it so as to customize the regulator for the user's specific needs. The technique must avoid instability and output voltage overshoot during the auto-compensation process. The auto-compensated system should have high bandwidth to provide fast transient responses and sufficient stability margin.